| 000 -LEADER |
|---|
| fixed length control field |
00661nam a2200217Ia 4500 |
| 005 - DATE AND TIME OF LATEST TRANSACTION |
|---|
| control field |
20200724135543.0 |
| 008 - FIXED-LENGTH DATA ELEMENTS--GENERAL INFORMATION |
|---|
| fixed length control field |
180712s9999 xx 000 0 und d |
| 020 ## - INTERNATIONAL STANDARD BOOK NUMBER |
|---|
| International Standard Book Number |
9780470823231 |
| 041 ## - LANGUAGE |
|---|
| Language of text/sound track |
English |
| 082 ## - DEWEY DECIMAL CLASSIFICATION NUMBER |
|---|
| Classification number |
621.381 |
| Author Mark |
BOL |
| DDC Edition number |
23 |
| 100 ## - MAIN ENTRY--PERSONAL NAME |
|---|
| Personal name |
Lin, Ming-Bo |
| 245 ## - TITLE STATEMENT |
|---|
| Title |
Digital system designs and practices : using Verilog HDL and FPGAs |
| Statement of responsibility, etc. |
/Ming-Bo Lin |
| 260 ## - PUBLICATION, DISTRIBUTION, ETC. |
|---|
| Place of publication, distribution, etc. |
Singapore |
| Name of publisher, distributor, etc. |
John Wiley & Sons. |
| Date of publication, distribution, etc. |
2008 |
| 300 ## - PHYSICAL DESCRIPTION |
|---|
| Extent |
xxiv, 809 p. |
| 500 ## - GENERAL NOTE |
|---|
| General note |
Includes index. |
| 650 ## - SUBJECT ADDED ENTRY--TOPICAL TERM |
|---|
| Topical term or geographic name entry element |
Digital electronics |
| 650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM |
|---|
| Topical term or geographic name entry element |
Field programmable gate arrays |
| 9 (RLIN) |
102887 |
| 650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM |
|---|
| Topical term or geographic name entry element |
Verilog (Computer hardware description language) |
| 9 (RLIN) |
102888 |
| 942 ## - ADDED ENTRY ELEMENTS (KOHA) |
|---|
| item type |
Books in Stacks (S) |
